STA Engineer
Core
STA Physical Design Engineer executing static timing analysis, DFT constraints, and timing closure for high-speed communication chips.
Role type
STA Physical Design Engineer
Builds
High-speed communication devices with highest throughput and lowest latency
Domain
Semiconductor / Physical Design / DFT
Required skills
Static Timing Analysis (STA), DFT constraints, RTL-driven constraints, Timing ECO generation, Physical Design flows, DFT flows (ATPG, Mbist, Ijtag), CDC analysis, EDA tools (Synopsys, Cadence)
Preferred skills
PNR, Physical verification, Silicon implementation understanding
Responsibilities
Execute DFT STA from RTL constraints to sign-off, generate timing ECOs for block and full chip levels, develop design flows, ensure DFT constraints quality assurance
Seniority
Mid-level (2-3 years experience)
