Senior Design Engineer, Coherent High Speed Interconnect
Core
Designing architecture and high-speed coherent interconnects (NVLINK-C2C) for mobile SoCs and GPUs to enable chiplet-based integration of NVIDIA GPUs, DPUs, and CPUs.
Role type
Senior IC hardware design engineer (interconnects)
Builds
High-speed coherent interconnects for chiplet-based integrated products
Domain
Semiconductor hardware design, high-speed interconnects, AI computing infrastructure
Deliverable
production ML models
Required skills
Electrical Engineering or Computer Engineering degree, 8+ years design experience, interconnect protocols (PCIe, CXL, AXI, CHI), link layer stacks (data link, physical), physical layer experience (DDR, LPDDR, PCIe, SerDes), architecture design, RTL design, performance analysis, power optimization, Verilog/System Verilog
Preferred skills
Advanced degrees (MS, PhD), mentoring junior engineers
Technologies
NVLINK-C2C, PCIe, CXL, AXI, CHI, DDR, LPDDR, SerDes, Verilog, System Verilog
Responsibilities
Design architecture for high-speed coherent interconnects, collaborate with architects and circuit designers, deliver class-leading interconnect solutions
Seniority
Senior, hands-on IC
