Staff Design Verification Engineer - Network Coherent Interconnect
Core
Design and validate the Arm NI-700 Non-Coherent Network-on-Chip Interconnect (NCI) for intelligent connected systems across mobile, networking, storage, server, HPC, automotive, and industrial applications.
Role type
Staff Design Verification Engineer (Network Coherent Interconnect)
Builds
Next generation of scalable/configurable interconnects optimized for ArmV8/ArmV9 processors
Domain
Semiconductor / SoC Design / Network-on-Chip
Required skills
Multiprocessing microarchitecture, cache coherence, bus protocols (AMBA5 CHI, AMBA4 ACE, AXI), System Verilog, UVM constrained-random testbenches, software engineering (OOP, data structures, algorithms), scripting (Python, Perl)
Preferred skills
Formal Verification testbenches
Technologies
System Verilog, UVM, Python, Perl, AMBA5 CHI, AMBA4 ACE, AXI
Responsibilities
Design and validate the NI-700 Non-Coherent Network-on-Chip Interconnect, create and debug System Verilog/UVM constrained-random testbenches, develop specifications for interconnect features, debug multiprocessing microarchitecture issues
Seniority
Staff, hands-on IC
