Senior Circuit Silicon Correlation DFT Engineer
Core
Senior DFT Engineer responsible for silicon characterization, correlation of post-silicon debug results to pre-silicon models, and root cause analysis for processor design failures in deep submicron technologies.
Role type
Senior IC DFT Engineer (Silicon Correlation)
Builds
Deep submicron processor designs and debug capabilities
Domain
Semiconductor / VLSI / Processor Design
Required skills
Design-for-test (DFT), ATPG, fault simulation, scan chain, BIST, on-chip scan compression, RAM circuit failure mechanisms, VLSI simulation tools, scripting (Python/Perl/Tcl), RTL/gate level verification
Preferred skills
Leadership experience, STA, circuit concepts, post-silicon data gathering, RAM testing methodologies
Technologies
VCS, Tessent, Python, Perl, Tcl, Make
Responsibilities
Generate ATPG patterns for silicon speed path debug; Correlate diagnosis results to map real design failures; Root cause failures and feed learnings to pre-silicon sign-off parameters; Study RAM circuit failure mechanisms and improve testing methods; Develop new DFT methodologies to analyze mis-correlation in logic and RAM.
Seniority
Senior, hands-on IC
