Senior I/O Subsystem Architect
Core
Define advanced chip interconnects and protocols for next-generation communications standards and products building on NVLink technology.
Role type
Senior I/O Subsystem Architect (Chip-to-Chip Interconnects)
Builds
Next generation chip-to-chip communication standards and products
Domain
Semiconductor / Hardware Interconnects
Required skills
Link layer architecture (Transaction, Data link, Physical), Interconnect protocols (PCIe, CXL, AXI, CHI), System architecture definition, Architectural modeling and validation, Technical trade-off analysis, Project lifecycle leadership
Preferred skills
None stated
Technologies
NVLink, PCIe, CXL, AXI, CHI
Responsibilities
Research and craft architecture solutions for chip-to-chip communication, Define interfaces and flows between NVLink C2C blocks and the rest of the chip, Drive implementation across design, verification, firmware and software teams, Collaborate with multi-functional teams to drive interconnect technology development and integration
Seniority
Senior, hands-on IC
