Senior Physical Design and Timing Engineer
Core
Drive physical design and timing of high-frequency, low-power DPUs and SoCs at block, chiplet, and full chip levels to achieve performance, power, and area targets.
Role type
Senior IC physical design and timing engineer
Builds
High-speed communication devices (DPUs, SoCs) for networking silicon
Domain
Semiconductor / Networking Silicon / ASIC Design
Required skills
Static Timing Analysis (STA), timing constraints management, timing convergence, physical design optimization (placement, routing, cell sizing, buffering, logic restructuring), logic synthesis, logical equivalence checking (LEC), Python/Tcl/Make scripting, EDA tools (Synopsys PrimeTime, Cadence Tempus)
Preferred skills
Domain-specific STA for CPUs/GPUs/Network processors, DFT timing closure, deep sub-micron technology knowledge, flow/automation development
Technologies
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Make
Responsibilities
Drive physical design and timing from RTL to GDS2 including synthesis, floor-planning, and ECO implementation; Analyze and optimize design constraints and synthesis parameters; Perform timing and power convergence analysis including crosstalk and noise analysis
Seniority
Senior, hands-on IC
