Physical Design CAD Engineer
Core
Developing physical design, synthesis, STA, and logic equivalence methodologies for high-speed networking chips and SOCs to ensure high quality and timely convergence.
Role type
Senior IC physical design CAD engineer
Builds
Networking silicon chips and System-on-Chips (SOCs)
Domain
Semiconductor / Networking
Required skills
Python, Perl, Tcl, Make scripting; physical design and optimization (placement, routing, cell sizing, buffering, logic restructuring); timing analysis and closure; power and noise analysis; process variation effect modelling; ECO implementation
Preferred skills
Synthesis, place and route, STA EDA tools (Synopsys DC/FC/PT, Cadence Innovus/Tempus); methodology definition / flow ownership
Technologies
Synopsys DC, Synopsys FC, Synopsys PT, Cadence Innovus, Cadence Tempus
Responsibilities
Develop physical design, synthesis, STA, and logic equivalence methodologies; Collaborate with block owners, full Chip STA engineers, and project managers; Solve state-of-the-art physical design problems; Participate in developing flow and tool methodologies for floorplan, power, clock distribution, P&R, timing analysis, closure, and back-end verification
Seniority
Mid-level, hands-on IC
