Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes
Core
Lead a team developing mixed-signal chips for high-speed I/O SerDes protocols (Ethernet, PCIe) used in gaming, AI, and autonomous driving SoCs.
Role type
Senior Digital Design Manager (Mixed-Signal High-Speed I/O SerDes)
Builds
Mixed-signal chips and key IPs for sophisticated SoCs
Domain
Semiconductor / Mixed-Signal High-Speed I/O
Required skills
Mixed-signal chip design, Verilog/SystemVerilog, logic design, circuit modeling in RTL, custom digital circuit design, adaptation algorithms (FFE, DFE, CTLE, CDR, offset cancellation), high-speed SerDes I/O digital design, UVM verification, static timing analysis, formal verification, front-end design flows (Lint/CDC/Synthesis/DFT/LEC/STA), silicon bring-up, PPA trade-off evaluation
Preferred skills
Leadership in mixed-signal design, technical strategy driving
Technologies
Verilog, SystemVerilog, UVM, Lint, CDC, Synthesis, DFT, LEC, STA
Responsibilities
Lead and mentor engineers in developing mixed-signal chips; Supervise planning and specification of algorithms and PPA trade-offs; Guide design of digital circuits including filters and analog calibration circuits; Ensure verification of digital designs using direct and random testing methodologies; Lead front-end design flows and coordinate with back-end teams for tape-outs; Drive silicon bring-up efforts and performance optimization; Collaborate with multi-functional teams to align technology roadmaps with business objectives; Establish and maintain standard methodologies for mixed-signal design and verification
Seniority
Senior, hands-on IC with leadership
