Principal Design Verification Engineer
Core
Lead front-end IP verification for complex HUB/Router designs, defining scalable methodologies and integrating AI-driven tools to improve quality and efficiency.
Role type
Principal Design Verification Engineer (System Architecture & AI)
Builds
High-performance computing silicon (HUB/Router IP) for server, data center, client, and embedded markets
Domain
Semiconductor / Computer Architecture / AI Engineering
Deliverable
production ML models
Required skills
Design verification strategy, system architecture, PCIe protocol verification, constrained-random verification, formal verification, emulation, coverage-driven verification, AI/ML integration, automation frameworks, data analysis, cross-functional leadership
Preferred skills
HUB/Router fabrics, coherency, virtualization, large-scale verification infrastructure, prompt engineering, workflow orchestration, debug infrastructure
Technologies
UVM, SystemVerilog, Python, AI/ML frameworks, Emulation platforms, Coverage tools
Responsibilities
Define and own DV test plans and methodologies for HUB/Router designs; Partner with architecture and design teams to build end-to-end verification strategies; Lead practical AI/ML-assisted verification initiatives (regression triage, failure clustering, stimulus optimization); Collaborate on AI tool adoption and workflow definition; Use data and dashboards to drive verification decisions; Mentor DV leads and engineers globally
Seniority
Principal, technical leadership & strategy
