DFT- SCAN/ATPG
Core
Design and implement DFT features (Scan, ATPG, MBIST) for next-gen AMD silicon processors and SoCs to ensure testability and defect identification.
Role type
Senior IC DFT/DFx Design Architect
Builds
DFT design features and test flows for complex SoC ASIC designs
Domain
Semiconductor / Digital IC Design
Required skills
ASIC DFX, Scan synthesis, ATPG, EDA tools (Fusion Compiler, Design Compiler, Spyglass), RTL quality check, Static timing analysis, Scripting (Perl, Python, TCL), Debug skills
Preferred skills
Low power concepts, Clock gating, Power gating, ICl Extraction, SSN, IJTAG, EDT, TestKompress, DC/AC scan development
Technologies
Fusion Compiler, Design Compiler, Spyglass, Lint, Tessent, TestKompress, Perl, Python, TCL
Responsibilities
Develop and implement cutting-edge DFX features including SCAN, ATPG, MBIST, BSCAN; Align on DFX requirements with Architecture and IP teams; Ensure correct DFT implementation in Scan/ATPG with Synthesis and PD teams; Develop and debug Scan/ATPG patterns and test flows; Create automated design flows for DFT implementation in complex SoC ASIC designs.
Seniority
Senior, hands-on IC
