Lead DFT Engineer
Core
Lead DFT Engineer responsible for scan architecture, ATPG pattern generation, test coverage analysis, yield debugging, and post-silicon bring-up to ensure first-pass silicon success.
Role type
Senior IC DFT Engineer
Builds
Integrated circuits (SOCs) and silicon designs
Domain
Semiconductor / VLSI / Hardware Design
Required skills
Scan Architecture, ATPG (Stuck-at, Transition, IDDQ), GLS/Timing/Power Aware Simulations, Test Coverage Analysis, Yield Analysis & Debug, Post Silicon Bring Up, Silicon Debug, SOC Tape-Outs
Preferred skills
Mentor testkompress, Synopsys Tetramax/DFTMAX, VCS simulation, Perl/Shell scripting, Verilog RTL design
Technologies
Mentor testkompress, Synopsys Tetramax, Synopsys DFTMAX, VCS, Perl, Shell, Verilog
Responsibilities
Perform scan insertion and ATPG pattern generation; Execute GLS, timing, and power-aware simulations; Conduct test coverage and cost reduction analysis; Perform yield analysis and debug for design root cause; Plan and execute post-silicon bring-up; Conduct extensive silicon debug for phasing closure; Manage multiple SOC tape-outs.
Seniority
Senior, hands-on IC
