ASIC/SOC DFT Engineer (Silicon Engineering)
Core
Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity.
Role type
Senior IC ASIC/SOC DFT Engineer
Builds
Next-generation ASIC chips for Starlink satellite and ground systems
Domain
Aerospace / Semiconductor Design
Deliverable
production ML models | product features | infrastructure
Required skills
Scan insertion, DFT setup, ATPG analysis, gate-level simulation, RTL/physical design flow, scripting (Python/Perl/bash), Verilog/SystemVerilog
Preferred skills
High reliability design, UPF, formal verification, DRC rule checking
Responsibilities
Evaluate design readiness for scan insertion via RTL and physical DRC tools; Integrate and verify DFT fabrics and IP within subsystems; Run and refine scan insertion recipes for maximum coverage; Run ATPG analysis to ensure quality scan chain construction; Debug non-timing and SDF annotated gate-level simulations; Create and validate ATPG content for post-silicon testing
Seniority
Mid-level, hands-on IC