ASIC/SOC DFT Engineer (Silicon Engineering)
Core
Developing next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
Role type
ASIC/SOC DFT Engineer (Silicon Engineering)
Builds
Next-generation ASIC chips for Starlink satellites and consumer receivers
Domain
Aerospace / Semiconductor Design
Deliverable
production ML models | product features | infrastructure
Required skills
Scan insertion, DFT setup, ATPG analysis, gate level simulation, RTL and physical design Scan DRC, Verilog/SystemVerilog, scripting (Python, Perl, Bash)
Preferred skills
ASIC design flow, physical design, verification, high reliability design, UPF, formal verification, DRC rule checking
Technologies
Verilog, SystemVerilog, Python, Perl, Bash, SDF, UPF
Responsibilities
Evaluate design readiness for scan insertion through RTL and physical design Scan DRC tools; Integrate and verify DFT fabrics and IP within subsystems; Run and evaluate scan insertion through synthesis tools; Run ATPG analysis to ensure quality scan chain construction; Run and debug non-timing and SDF annotated gate level simulations; Collaborate with circuit physical design, ATPG, and manufacturing teams
Seniority
Mid-level, hands-on IC