ASIC Physical Design Engineer
Core
Design, test, and deploy advanced hardware for an ultra low latency team, collaborating across trading, networking, and research infrastructure.
Role type
Senior ASIC Physical Design Engineer (full-stack chip design)
Builds
Advanced hardware chips for trading, networking, and research infrastructure
Domain
Semiconductor / Hardware Engineering
Deliverable
production ML models
Required skills
Physical design flow ownership (floor planning, place and route, timing closure, physical verification, power analysis), RTL design and coding, cross-domain design reasoning, software engineering techniques, high-level programming (Python, C++, Haskell)
Preferred skills
Experience with hardware development toolchains, familiarity with OCaml
Technologies
Hardcaml, OCaml, Python, C++, Haskell
Responsibilities
Lead physical design expertise while thinking like a chip designer, own the PD flow end-to-end, read and write RTL, reason about front-end/back-end design decisions, use software engineering to improve hardware design processes
Seniority
Senior, hands-on IC
