ASIC Design STA Engineer
Core
Develop timing constraints and verify timing for large System-on-Chip (SoC) designs with multiple physical blocks and clock domains.
Role type
Senior ASIC Design STA Engineer
Builds
Large SoCs for AI, data centers, PCs, gaming, and embedded systems
Domain
Semiconductor / ASIC Design
Required skills
Static Timing Analysis (STA), SDC development, EDA tool proficiency, TCL scripting, RTL quality metrics, hierarchical design flows
Preferred skills
Synopsys Design Compiler, Synopsys PrimeTime, Spyglass, Fishtail, pre-route timing checks, QoR cleanup, flat/hierarchical flows
Technologies
Synopsys Design Compiler, Synopsys PrimeTime, Spyglass, Fishtail, TCL, Linux
Responsibilities
Develop complex multi-mode/multi-corner timing constraints; maintain RTL quality metrics in hierarchical designs; implement pre-route timing checks and QoR cleanup; collaborate on synthesis and STA workflows; automate timing processes using TCL scripts
Seniority
Senior, hands-on IC
