ASIC Engineer
Core
Design, test, and deploy advanced hardware designs for ultra low latency systems, working on both FPGA and ASIC technologies.
Role type
Senior IC ASIC Engineer
Builds
Ultra low latency trading and networking infrastructure
Domain
Fintech hardware engineering
Deliverable
production ML models | product features
Required skills
RTL design and verification, ASIC design flows (Synopsys/Cadence), formal verification, high-level programming (Python/C++/Java/Haskell), hardware development toolchain usage
Preferred skills
Experience with Hardcaml/OCaml, software engineering techniques for hardware
Technologies
Synopsys, Cadence, Hardcaml, OCaml, Python, C++, Java, Haskell
Responsibilities
Design front-end RTL and perform synthesis, execute back-end physical design, conduct verification including formal methods, collaborate with trading and research infrastructure teams
Seniority
Senior, hands-on IC
