Sr. Module Engineer, Hybrid Bonding
Core
Develop and scale next-generation hybrid bonding technologies for advanced semiconductor packaging applications including memory, chiplets, AI accelerators, photonics, and heterogeneous integration platforms.
Role type
Senior IC process engineer (hybrid bonding)
Builds
Next-generation 3D integration and HBM stacking solutions
Domain
Semiconductor manufacturing / Advanced packaging
Required skills
Die-to-wafer hybrid bonding process development, Surface preparation, Plasma activation, Die placement, Alignment and overlay control, Bonding temperature and pressure optimization, Post-bond annealing, Cu-Cu and dielectric-dielectric interconnect formation, Process integration, Yield and defect reduction, Metrology and characterization, DOE methodologies, Statistical process control, Equipment engineering collaboration
Preferred skills
Experience with memory architectures, Chiplet-based systems, Silicon interposers, System-on-Wafer platforms, Co-packaged optics (CPO)
Technologies
CSAM, X-ray inspection, FIB/SEM, AFM, Optical metrology, Electrical test structures
Responsibilities
Develop and optimize die-to-wafer (D2W) hybrid bonding processes for advanced packaging applications, Establish process windows for surface preparation, plasma activation, die placement, alignment and overlay control, bonding temperature and pressure optimization, and post-bond annealing, Drive Cu-Cu and dielectric-dielectric interconnect formation with focus on electrical performance and reliability, Support integration of hybrid bonding into memory architectures, chiplet-based systems, silicon interposers, system-on-wafer platforms, and co-packaged optics (CPO), Identify root causes of bond voids, die shift, overlay errors, non-uniform bonding, and particle contamination, Drive bonding quality characterization using CSAM, X-ray inspection, FIB/SEM, AFM, optical metrology, and electrical test structures
Seniority
Senior, hands-on IC