Process Engineer – Die to Wafer Hybrid Bonding
Core
Developing and optimizing die-to-wafer hybrid bonding processes for silicon photonics and co-packaged optics to enable photonic-electronic co-integration for AI and HPC systems.
Role type
Hands-on IC process engineer (die-to-wafer hybrid bonding)
Builds
Next-generation optical interconnects and co-packaged optics for AI/HPC
Domain
Semiconductor manufacturing / Silicon photonics / Materials science
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Die-to-wafer or wafer-to-wafer bonding, Thin-die handling and alignment-critical processes, Direct process engineer experience on mainstream semiconductor equipment, 2.5D/3D integration, Bond interface physics, Alignment and overlay fundamentals, Mechanical behavior of thin and fragile dies, Statistical analysis and process control (DOE, SPC, JMP)
Preferred skills
None stated
Technologies
None stated
Responsibilities
Develop die-to-wafer hybrid bonding processes including surface preparation, plasma activation, high-accuracy die placement and alignment, and post-bond characterization, Integrate D2W bonding with adjacent process modules such as dicing, die preparation, die thinning, and inter-die gap fill and planarization, Design and execute DOE-driven experiments to understand process limits, sensitivities, and trade-offs, Own process optimization, perform failure analysis and characterization, and drive continuous engineering improvement
Seniority
Senior, hands-on IC
