Staff Digital Design Engineer
Core
Optimize and implement advanced DSP algorithms and circuits for 200+Gbps SerDes systems, focusing on power efficiency and optimization for next-generation connectivity solutions.
Role type
Staff Digital Design Engineer (SerDes/DSP)
Builds
High-speed SerDes transceivers for data center networking, wireless telecommunications, and aerospace/defense
Domain
Semiconductor / High-speed serial interfaces
Required skills
Digital signal processing (DSP) algorithms, RTL design (SystemVerilog), ASIC front-end design tools (lint, synthesis, STA), Clock domain crossing, Power analysis and reduction techniques, Simulation and modeling of DSP algorithms
Preferred skills
Experience with high-speed serial interfaces (Ethernet, PCIe), Understanding of digital design techniques
Technologies
SystemVerilog, ASIC tools, SerDes
Responsibilities
Collaborate with architects and verification engineers to implement new DSP features, Implement DSP algorithms for equalization, filtering, and sequence detection, Develop comprehensive documentation on DSP algorithm interactions
Seniority
Staff, hands-on IC
