Senior DFT Engineer
Core
Own Design-for-Test on customer SoCs end-to-end, covering DFT architecture, scan/ATPG, memory BIST, boundary scan, pattern validation, and production test hand-off.
Role type
Senior IC DFT Engineer
Builds
ASIC and COT designs for fabless companies and OEMs
Domain
Semiconductor / Integrated Circuit Design
Required skills
DFT methodologies (scan, ATPG, at-speed test, memory BIST, I/O DFT), Scan insertion, ATPG for stuck-at/transition-delay/bridging/IDDQ, DFT DRC analysis and coverage debug, Memory BIST, JTAG IEEE 1149.1/1149.6/1500, Gate-level simulation, Formal equivalence checking, Perl/Tcl/UNIX scripting
Preferred skills
Siemens Tessent (ScanPro/TestKompress/LBIST), Advanced-node experience (7nm and below), Python
Technologies
Synopsys DFT Compiler, TestMAX (TetraMAX), SpyGlass DFT, Siemens Tessent, Perl, Tcl, UNIX, Python
Responsibilities
Design and implementation of DFT features, End-to-end DFT flow ownership from concept to tape-out to production, Gate-level simulation setup and runs, Formal equivalence checking
Seniority
Senior, hands-on IC
