Staff CAD Layout Automation and Methodology Engineer
Core
Develop, integrate, maintain, and deploy PDK Physical Design components, IP, and methodologies for Analog, Mixed-Signal, and Digital design teams across mature and advanced technology nodes.
Role type
Staff CAD Layout Automation and Methodology Engineer
Builds
PDK Physical Design flows, reference components, supporting utilities, and design enablement collateral
Domain
Semiconductor / IC Physical Design / EDA
Required skills
CMOS/planar/FinFET fundamentals, IC physical design and layout methodologies, Virtuoso environment, UNIX/Linux shell scripting, Python, Perl, Cadence SKILL programming, foundry technology documentation interpretation
Preferred skills
Full chip layout/physical design development and Tapeout experience, automation and productivity tool development
Technologies
Virtuoso, Cadence SKILL, Python, Perl, UNIX/Linux
Responsibilities
Develop and adapt PDK Physical Design flows and design enablement collateral; Define and maintain physical-design methodologies and configurations; Develop technology-dependent layout structures and reference components; Translate foundry technology requirements into robust PDK flows; Collaborate with foundries, EDA vendors, and design teams
Seniority
Staff, hands-on IC
