CareerPlan

Principal Package Design Engineer

Tempe, Arizona, usFull-time2026-10-19 → 2026-11-11

Core

Design and develop package and interconnect methods for power SiP/modules, flip-chip LGA, and multi-chip modules with substrate or embedded die/capacitor for consumer, industrial, and automotive applications.

Role type

Principal Package Design Engineer

Builds

Power SiP modules, flip-chip LGA packages, and multi-chip modules

Domain

Semiconductor packaging and interconnects

Required skills

Power SiP/module design, wafer level packaging, flip-chip LGA packaging, assembly process knowledge, qualification methods, SPC, statistical analysis, DOE execution, OSAT/CM management, process integration, production ramp-up monitoring, package design rules establishment

Preferred skills

Cu FSM/BGBM technologies knowledge

Technologies

SPC software, statistical analysis software

Responsibilities

Design and develop package and interconnect methods; Qualify package technologies for consumer, industrial, and automotive applications; Benchmark and select materials, processes, and subcontractors; Develop and run DOE to optimize processes; Resolve process integration issues; Establish production controls; Ensure smooth transition into production; Address customer complaints; Develop and maintain technical expertise on packaging innovations; Participate in packaging roadmap development; Establish and maintain package design rules

Seniority

Principal, hands-on IC