Senior IC Packaging Engineer
Core
Define and drive high-performance, low-power packaging architectures for advanced IC and System-in-Package (SiP) products, leading from early technology path finding through production ramp.
Role type
Senior IC Packaging Engineer (System-in-Package & Chiplet Architect)
Builds
Advanced IC and SiP packages for AI infrastructure and security hardware
Domain
Semiconductor packaging, heterogeneous integration, chiplet-based design
Required skills
IC packaging architecture, chiplet-based design (UCIe), silicon interposers, RDL, flip-chip BGA, high-speed SerDes (PCIe, CXL, LPDDR5), substrate stack-up definition, DFM guidelines, SI/PI trade-offs, thermal/mechanical/reliability optimization, OSAT/foundry collaboration
Preferred skills
EDA tools (Cadence Allegro APD, HFSS, SIwave, Ansys Designer), new packaging methodology development
Technologies
UCIe, PCIe Gen5, LPDDR5, RDL, silicon interposers, flip-chip BGA, 2.5D fan-out
Responsibilities
Own package architecture and technology roadmap; Lead chiplet-based packaging strategies; Perform hands-on package design and physical layout; Define substrate stack-ups and DFM guidelines; Drive SI/PI, thermal, mechanical, and reliability trade-offs; Lead external engagement with OSATs and foundries; Influence product roadmap and investment decisions.
Seniority
Senior, hands-on IC
