Senior Staff Digital Design Engineer
Core
Develop micro-architecture and front-end digital design deliverables for power management ASICs from concept to silicon.
Role type
Senior Staff Digital Design Engineer (Power Management ICs)
Builds
Power management ASICs and mixed-signal integrated circuits
Domain
Semiconductor / Power Management ICs
Required skills
Micro-architecture definition, RTL coding (Verilog/System Verilog), Logic synthesis, Static Timing Analysis (STA), Power estimation, Clock Domain Crossing, DFT architecture, Silicon debug, Register design, Protocol implementation (I2C, PMBUS)
Preferred skills
Mixed-signal IC design experience, Block and top-level timing constraints, Design for Test (DFT) strategy, Work-around solutions for device errata
Technologies
Verilog, System Verilog, I2C, PMBUS, OTP, MTP, Efuse
Responsibilities
Lead optimized digital blocks design meeting functional and low power constraints; Define digital/analog boundaries and micro-architectures; Handle Clock Domain Crossing across multiple domains; Lead Logic Synthesis, Formal verification, Power estimation, and STA; Perform silicon debugs and root cause analysis; Interface with P&R for digital hand-off; Produce high-quality documentation for owned blocks.
Seniority
Senior Staff, hands-on IC design
