(Senior) Layout Engineer (f/m/d)
Core
Create block-level and top-level layout design for new and next generation ICs, integrated sensors, and mixed signal technologies.
Role type
Senior IC Layout Engineer (Analog/Mixed Signal)
Builds
Sensor ASICs, Sensor ASSPs, Position Sensors, LiDAR ASICs, and Environmental Sensors
Domain
Semiconductor / Automotive Sensors / Analog IC Design
Required skills
Analog IC layout design, Cadence Virtuoso, Calibre DRC/LVS, parasitic extraction, LVS verification, DRC verification, yield optimization, manufacturability analysis
Preferred skills
Semiconductor device physics, microelectronics, English (fluent), German (fluent)
Technologies
Cadence Virtuoso, Calibre
Responsibilities
Create block-level and top-level layout design, Own layout design for multiple tape outs of ICs and test structures, Implement analog layout dependent design for yield and manufacturability, Ensure block- and top-level Design Rule Checks (DRC) and Layout versus Schematics Checks (LVS), Support block-level and top-level specifications, Deliver optimized layouts that are first time right
Seniority
Senior, hands-on IC