Principal Digital Design Engineer
Core
Develop, debug, and verify advanced digital power management ICs in pre and post silicon environments.
Role type
Principal Digital Design Engineer (IC)
Builds
Industry leading digital power management chips
Domain
Semiconductor / Power Management ICs
Required skills
Verilog, System Verilog, CDC/RDC/LINT debugging, gate level simulation, serial interface design (I2C, I3C, SPI, I2S), Cadence/Synopsys flows, design automation scripting, technical mentorship
Preferred skills
Python/Perl scripting, ARM Cortex M-series architecture, mixed-signal design basics, digital backend flow (synthesis/STA/P&R), full design flow experience, PMBus/SMBus/AVSBus/SVID/SVI3
Technologies
Verilog, System Verilog, Cadence, Synopsys, Python, Perl, ARM Cortex M
Responsibilities
Develop and verify digital designs in pre and post silicon environments; Write tests to verify bulk design intent; Develop and improve automation scripts; Manage assigned design blocks; Research and present new design tools; Mentor junior engineers; Lead digital design in projects
Seniority
Principal, hands-on IC with technical leadership
