Staff Design Engineer, Power Management, Clock & Reset
Core
Develop micro-architecture and RTL design for power management, voltage control, clock, and reset technologies in next-generation System-on-Chip (SoC) solutions.
Role type
Staff IC digital design engineer (SoC power & clock)
Builds
Micro-architecture and RTL for critical IP and subsystems enabling efficient power management and reliable SoC operation
Domain
Semiconductor / SoC Design
Required skills
SoC power management, digital control logic, low-power design, RTL design (Verilog/SystemVerilog), synthesis, timing analysis, clock domain crossing (CDC), reset domain crossing (RDC)
Preferred skills
Arm-based SoC architecture, Unified Power Format (UPF), physical implementation, design for test (DFT), scripting (Python/Perl/Tcl), AI-assisted hardware design tools
Technologies
Verilog, SystemVerilog, UPF, Python, Perl, Tcl
Responsibilities
Develop micro-architecture and RTL for power/clock/reset subsystems; Translate architectural requirements into detailed design specs; Design control logic for power-state transitions and clock sequencing; Ensure design quality via RTL reviews, synthesis, and timing analysis; Collaborate on test planning, functional debug, and integration; Improve design methodologies and automation flows; Participate in technical design reviews and knowledge sharing
Seniority
Staff, hands-on IC with mentorship