Senior Digital Verification Engineer
Core
Design and develop scalable, reusable verification environments for complex Digital and Mixed-Signal ASICs to ensure robust product quality and accelerate first silicon bring-up.
Role type
Senior IC digital verification engineer
Builds
Consumer and automotive integrated circuits
Domain
Semiconductor / ASIC design
Required skills
UVM, formal verification, directed verification, VHDL/Verilog, Python, Tcl, Mixed-Signal modeling, UPF, simulation/verification EDA tools
Preferred skills
AI-assisted engineering workflows, Analog/mixed-signal modeling (wreal, MATLAB/Simulink, SystemC), Power-aware verification
Technologies
UVM, Python, Tcl, VHDL, Verilog, SystemC, MATLAB, Simulink, wreal
Responsibilities
Design scalable verification environments for complex ICs, Apply functional and formal verification methodologies, Collaborate in a globally distributed engineering network, Participate in concept definition through qualification phases, Document and improve verification processes and best practices
Seniority
Senior, hands-on IC
