(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die (Experienced in Power or Gan is requried)
Core
Design and develop package and interconnect methods for Power SiP/modules, wafer level, flip-chip, and multi-chip module packaging.
Role type
Staff Package Design Engineer (Power/GaN)
Builds
Power SiP/modules, wafer level packages, flip-chip interconnects, and panel level packages for consumer, industrial, and automotive applications.
Domain
Semiconductor packaging and power electronics
Required skills
Power SiP/module design, wafer level packaging, flip-chip packaging, assembly process qualification, DOE optimization, SPC, statistical analysis, material selection, OSAT/CM management
Preferred skills
GaN packaging, wire-bonding, multi-chip module technologies
Technologies
DOE, SPC, statistical analysis software
Responsibilities
Benchmark and qualify materials, processes, and assembly subcontractors; develop and optimize processes with OSAT/CM; qualify new packages and resolve customer complaints; ensure smooth production transition and ramp-up monitoring; participate in packaging roadmap development; establish and maintain package design rules.
Seniority
Staff, hands-on IC with strategic oversight
