Sr Staff Digital Design Engineer
Core
Develop, debug, and verify advanced digital power management ICs in pre and post silicon environments.
Role type
Senior Staff IC Digital Design Engineer
Builds
Industry-leading digital power management chips
Domain
Semiconductor / Power Management ICs
Required skills
Verilog, System Verilog, CDC/RDC/LINT debugging, gate-level simulation, serial interface design (I2C, I3C, SPI, I2S), Cadence/Synopsys flows, design automation scripting, technical mentorship
Preferred skills
Python/Perl scripting, ARM Cortex M-series architecture, mixed-signal design exposure, digital backend flow (synthesis/STA/P&R), full design flow experience
Responsibilities
Develop and verify digital designs in pre and post silicon environments; Write tests to verify bulk design intent; Develop and improve design automation scripts; Manage assigned design blocks regarding requirements, architecture, and implementation; Research and present new design tools; Act as technical mentor for junior engineers; Represent digital design as functional lead in projects
Seniority
Senior Staff, hands-on IC with technical leadership
