Staff Design Verification Engineer
Core
Verification of advanced memory data buffer products (DDR6 and future generations) for data center, AI, and cloud computing applications.
Role type
Staff Design Verification Engineer
Builds
High-bandwidth, power-efficient memory solutions for intensive computing environments
Domain
Semiconductor / Memory Interfaces
Required skills
SystemVerilog, UVM, verification planning, functional verification, coverage analysis, testbench development, debugging, technical leadership
Preferred skills
DDR4/DDR5 experience, verification methodology improvement, mentoring
Technologies
SystemVerilog, UVM, DDR6
Responsibilities
Drive verification activities for complex digital designs at block and system level; Develop and execute verification plans based on functional and performance specifications; Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches; Develop verification tests, functional coverage, checkers, and other verification components; Take ownership of verification environments and verification execution for assigned blocks and features; Drive and monitor coverage to ensure verification goals are achieved; Analyze verification results, debug failures, and identify functional or design issues; Serve as a technical resource within the team, providing guidance on complex verification problems and sharing best practices
Seniority
Staff, hands-on IC with technical leadership (via careerplan.io/jobs/744000152991224-staff-design-verification-engineer-at-renesas-electronics)
