Senior Staff AMS Design Verification Engineer
Core
Senior project lead responsible for guaranteeing specification compliance of analog & mixed signal designs through advanced verification methodologies to achieve first-pass silicon success.
Role type
Senior Staff IC analog & mixed-signal design verification engineer (team lead)
Builds
Complex integrated circuits and sub-systems for automotive, industrial, infrastructure, and IoT markets
Domain
Semiconductor / Analog & Mixed-Signal Integrated Circuits (via careerplan.io/jobs/744000152831319-senior-staff-ams-design-verification-engineer-at-renesas-electronics)
Deliverable
production ML models | product features
Required skills
Analog & mixed-signal circuit concepts, System Verilog, UVM, RTL coding, ASIC design methodology, UNIX/Perl/TCL scripting, verification planning, coverage analysis, testbench development, team leadership, technical mentoring
Preferred skills
Modeling power converters, behavioral modeling of analog blocks using System Verilog (RNM) and Verilog AMS, experience with mixed signal verification environments
Technologies
Cadence Virtuoso, xCelium, Incisive, vManager, IMC, System Verilog, UVM, Verilog AMS, UNIX shell scripting, Perl, TCL
Responsibilities
Lead analog & mixed signal verification of complex ICs, develop verification strategy and environments, debug RTL for design intent, mentor verification team, delegate project tasks, participate in cross-functional reviews, drive strategic changes in analog verification function
Seniority
Senior Staff, hands-on IC with team leadership