Senior Design Verification Engineer
Core
Confirm accuracy of analog and mixed-signal electronic designs and integrated circuits before pattern generation and mask development.
Role type
Senior IC design verification engineer (analog/mixed-signal)
Builds
Analog and mixed-signal electronic parts, components, and integrated circuitry
Domain
Semiconductor hardware design (analog/mixed-signal)
Deliverable
production ML models | product features
Required skills
SystemVerilog, VHDL, UVM, gate-level simulation, formal verification, analog concepts, behavioral modeling, testbench creation, debugging, spec definition, verification strategy, coverage monitoring, checkers, DV environment ownership
Preferred skills
Motor control (BLDC/BSM), Cadence tools, firmware verification
Technologies
SystemVerilog, VHDL, UVM, Cadence
Responsibilities
Define verification strategy and plans ensuring 100% spec-to-regression traceability; develop and maintain comprehensive verification environments; collaborate with architecture, RTL, PD, DFT, and analog teams; own IP/full-chip verification from spec definition to post-silicon closure; debug and solve customer issues.
Seniority
Senior, hands-on IC