Junior Digital Verification Engineer
Core
Design and develop scalable, reusable verification environments for complex Mixed-Signal and System-on-Chip (SoC) ASICs to ensure product quality and accelerate first silicon bring-up.
Role type
Junior Digital Verification Engineer (ASIC/SoC)
Builds
Consumer and automotive integrated circuits
Domain
Semiconductor / Mixed-Signal SoC Design
Deliverable
production ML models | product features
Required skills
UVM, formal verification, directed verification, Python, Tcl, UPF, SystemC, MATLAB/Simulink, wreal
Preferred skills
AI-assisted engineering workflows, analog and mixed-signal modeling techniques, power-aware verification methodologies
Responsibilities
Design and develop scalable verification environments, apply functional and formal verification methodologies, collaborate in a global engineering network, document and improve verification processes
Seniority
Junior, entry-level IC engineer
