Senior ASIC Digital Lead - ATPG & Methodology (f/m/div.)
Core
Senior technical lead responsible for digital ASIC design scope, DFT/ATPG integration, and test flow stability across complex mobility system projects.
Role type
Senior IC ASIC Digital Lead (ATPG & Methodology)
Builds
Digital ASIC designs for modern mobility systems
Domain
Automotive semiconductor design and test
Deliverable
production ML models | product features
Required skills
Digital ASIC design, top-level integration, ATPG, test methodologies, coverage analysis, failure analysis, Python/Tcl/shell scripting, cross-functional coordination
Preferred skills
Experience coordinating external development partners, developing automation solutions for test flows
Technologies
ATPG tools, Python, Tcl, shell
Responsibilities
Coordinate specification, development, and integration of digital design scope; ensure DFT and ATPG aspects are integrated to meet coverage targets; drive ATPG/DFT flow stability and continuous improvement; analyze silicon data and defect signatures to identify root causes; develop automation solutions to enhance efficiency and standardization
Seniority
Senior, hands-on IC