Verification Staff Engineer - Analog Mixed-Signal
Core
Execute and own design verification activities for analog and mixed-signal integrated circuits to ensure first-pass silicon success and compliance with performance, power, and schedule requirements.
Role type
Senior IC analog mixed-signal verification engineer
Builds
Production verification environments, testbenches, checkers, and coverage metrics for mixed-signal IPs
Domain
Semiconductor design, analog/mixed-signal circuits, verification engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production verification environments and testbenches
Required skills
SystemVerilog, UVM, constrained randomization, metric-driven verification, analog/mixed-signal circuit concepts, reading analog schematics, VerilogAMS, RTL coding, ASIC design methodology, UNIX/Perl/TCL scripting
Preferred skills
Modeling power converters, biasing networks, power regulators, bandgaps, amplifiers, comparators, data converters, mixers, multiplexers, switches
Technologies
Cadence Virtuoso, xCelium, Incisive, vManager, IMC, SystemVerilog, UVM, VerilogAMS, Perl, TCL
Responsibilities
Develop efficient, reusable verification environments and testbench structures; contribute to verification strategies for mixed-signal IPs; debug RTL for design intent; provide technical guidance to team members; achieve verification completeness against coverage goals
Seniority
Senior, hands-on IC