Senior Engineer- DEG Layout
Core
Senior IC layout engineer responsible for analog, mixed-signal, and custom digital block layout design, verification, and tape-out support in advanced CMOS processes.
Role type
Senior IC layout engineer (analog/mixed-signal)
Builds
Custom analog/mixed-signal blocks (PLL, ADC, DAC, LDO, Bandgap, etc.) and full chip layouts
Domain
Semiconductor IC design (Analog/Mixed-Signal)
Required skills
Analog layout design, Mixed-signal layout, Custom digital block layout, LVS/DRC verification, EM/IR/I-drop analysis, Parasitic extraction, Auto-placement and routing, Skill coding/automation, Tape-out support (via careerplan.io/jobs/43282293-senior-engineer-deg-layout-at-micron)
Preferred skills
AI tool integration for layout optimization, Multiple tape-out experience
Technologies
Cadence VLE/VXL, Mentor Calibre DRC/LVS
Responsibilities
Design and develop critical analog and mixed-signal layouts; Perform layout verification (LVS, DRC, Antenna, Shield, Matching, Latch-up, EM/IR); Guide team members on sub-block layouts; Reduce layout effort using AI tools; Lead planning and scheduling for multiple projects.
Seniority
Senior, hands-on IC
