Senior Staff Engineer, Design Verification (Power & Analog ICs)
Core
Lead verification of digital content embedded within power, analog, and mixed-signal IC products, ensuring design meets functional requirements before tape-out.
Role type
Senior Staff Individual Contributor Design Verification Engineer
Builds
Scalable verification environments, testbenches, agents, and coverage models for complex semiconductor products
Domain
Semiconductor / Power & Analog ICs / Mixed-Signal
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, verification architecture, coverage closure, formal verification, assertion-based verification, debug methodologies, RTL design, microarchitecture, clock/reset management, serial interfaces (SPI, I2C, UART), DFT, ATPG, gate-level simulation, scripting (Python/TCL/Perl/Shell)
Preferred skills
FPGA/emulation techniques, silicon bring-up, device evaluation, root-cause analysis, timing-aware verification, post-layout verification
Technologies
SystemVerilog, UVM, Python, TCL, Perl, Shell, FPGA, Emulation
Responsibilities
Own block-level and full-chip digital verification strategy; develop verification plans and coverage goals; design and develop SystemVerilog/UVM-based testbenches and environments; execute regression, triage, and debug; collaborate on analog-digital interaction models; support DFT and production-test vector development; mentor engineers and drive verification methodology; provide sign-off assessments to leadership
Seniority
Senior Staff, hands-on IC
