Senior Digital Design Verification Engineer
Core
Independently own verification of complex digital blocks and major SoC features for power management integrated circuits, covering planning through closure.
Role type
Senior IC digital design verification engineer
Builds
Power management SoCs integrating digital control, telemetry, fault management, and communication interfaces for AI, datacenter, enterprise computing, and networking applications.
Domain
Semiconductor / Power Management ICs / Digital Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained random verification, functional coverage, SystemVerilog Assertions, RTL debugging, testbench development, regression automation, scripting (Python/Bash/Perl/Tcl), digital design fundamentals (FSMs, clock domains)
Preferred skills
SoC verification, mixed-signal verification, embedded processor interfaces, control protocols (PMBus, I2C, SPI), formal verification, gate-level simulation, verification infrastructure improvement
Technologies
SystemVerilog, UVM, Cadence Xcelium, SimVision, Synopsys VCS, Verdi, Python, Bash, Perl, Tcl
Responsibilities
Develop feature-based verification plans from specifications; build and extend reusable UVM environments; create constrained random and targeted tests; drive coverage closure; debug RTL and testbench failures; automate regression and reporting workflows; provide technical guidance to junior engineers
Seniority
Senior, hands-on IC
