Senior/Staff Engineer, Design Verification
Core
End-to-end verification execution for complex digital IP and subsystems from specification to sign-off.
Role type
Senior/Staff IC Design Verification Engineer
Builds
Scalable, reusable UVM-based verification environments and robust verification plans/checkers for SoC integration.
Domain
Semiconductor / Digital SoC Verification
Deliverable
production ML models | product features
Required skills
UVM-based testbench architecture, SystemVerilog, assertions (SVA), constrained-random verification, coverage closure, EDA toolkits, C/C++, Shell scripting
Preferred skills
AI/ML-based verification tools, Python/Perl/TCL scripting, formal verification, high-speed IP (H.264, security, safety-critical)
Technologies
UVM, SystemVerilog, SVA, EDA tools, Python, Perl, TCL, C, C++, Shell
Responsibilities
Define IP-level verification strategies and test plans; Develop scalable UVM environments; Lead functional, code, assertion, and cross-coverage closure; Apply AI/ML techniques to optimize regression; Collaborate with RTL/Architecture/Emulation teams; Develop advanced checkers, scoreboards, and protocol monitors; Mentor junior engineers; Support GLS, low-power verification, and post-silicon debug.
Seniority
Senior/Staff, hands-on IC
