Senior/Staff Engineer, Design Verification
Core
Senior IP Design Verification Engineer building verification environments from scratch for next-generation microcontrollers and microprocessors.
Role type
Senior IC Design Verification Engineer (SoC/IP)
Builds
Reusable IPs for next-generation microcontrollers and microprocessors
Domain
Semiconductor / SoC Design / Digital IP
Deliverable
production ML models | product features
Required skills
UVM-based testbench architecture, SystemVerilog, metric-driven verification, coverage closure, constraint random verification, directed test methodologies, assertion-based verification (SVA), protocol monitoring, post-silicon debugging, EDA toolkits
Preferred skills
AI/ML-based verification tools, Python/TCL/Perl scripting, formal verification, high-speed IP verification
Technologies
UVM, SystemVerilog, SVA, EDA tools, AI/ML verification tools
Responsibilities
Define and drive IP-level verification strategies including test plans and coverage models, develop scalable UVM-based verification environments, lead functional and code coverage closure, apply AI/ML techniques to accelerate coverage convergence, drive constraint random and directed test methodologies, collaborate with RTL and Architecture teams, develop advanced checkers and scoreboards, mentor junior engineers, support Gate-Level Simulation and post-silicon debug
Seniority
Senior, hands-on IC
