Senior Staff Engineer, Low Power & Formal Equivalence Verification (VCLP / FEV)
Core
Lead Low Power (Power Intent) and Formal Equivalence Verification (FEV/LEC) activities for complex ASIC/SoC programs from RTL to tapeout.
Role type
Senior Staff Engineer, Low Power & Formal Equivalence Verification
Builds
ASIC/SoC designs with verified low-power integrity and functional correctness
Domain
Semiconductor (ASIC/SoC) / Digital Design & Verification
Required skills
UPF/CPF low-power methodologies, Formal Equivalence Verification (FEV/LEC), RTL-to-tapeout flow expertise, Power domain/state specification, Isolation/retention/level shifters, Synthesis/DFT/STA/ECO flows, Tcl/Python/Perl/Shell scripting
Preferred skills
Advanced-node technology (7nm and below), Physical Design/PDN/STA knowledge, Full-chip SoC tapeout support
Technologies
UPF, CPF, FEV/LEC tools, Tcl, Python, Perl, Shell
Responsibilities
Define and maintain low-power architecture and power intent; Execute formal equivalence checks at RTL, Synthesis, DFT, and Physical Design milestones; Debug power-intent and equivalence failures; Develop automation for verification efficiency; Drive low-power issue closure and tapeout readiness
Seniority
Senior Staff, hands-on IC
