Design Verification Manager
Core
End-to-end design verification (DV) and post-silicon debugging for ultra-low-power System-on-Chips (SoCs) and intellectual properties (IPs) serving industrial, automotive, and embedded sectors.
Role type
Senior Design Verification Manager (SoC/IP)
Builds
Ultra-low-power SoCs and high-performance digital/analog IPs
Domain
Semiconductor design, embedded systems, automotive safety (ISO 26262/ISO 21434)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM/SystemVerilog, Specman, GLS/PAGLS/UPFL, C, Perl, Python, RTL/PARTL verification, formal verification, post-silicon debugging, ISO 26262/ISO 21434 compliance, cross-functional team leadership
Preferred skills
AI/ML-based DV, ARM power-aware simulation, Cadence tools (Xcelium, vManager, Formal JG), analog/mixed-signal verification, clock domain crossing (CDC)
Technologies
UVM, SystemVerilog, Specman, GLS, PAGLS, UPF, C, Perl, Python, Xcelium, vManager, Formal JG
Responsibilities
Define verification strategies and plans ensuring traceability between specifications and regression; conduct IP, SubSystem, and SoC verification in RTL/PARTL and GLS/PAGLS modes; own the DV environment including test benches, UVC integration, and coverage monitors; provide final SoC DV signoff based on regression results and coverage metrics; actively participate in customer reviews and certification processes; collaborate with Architecture, RTL, PD, DFT, Systems, Analog, Firmware, and Application teams.
Seniority
Senior, hands-on IC with management responsibilities
