Senior Staff Digital Verification Engineer
Core
Development and verification of digital sections for leading-edge memory data buffer chips (DDR5, DDR6+) for datacenter AI and cloud computing.
Role type
Senior Staff Digital Verification Engineer
Builds
Memory interface products for datacenters
Domain
Semiconductor / Memory Interfaces / Datacenter AI
Deliverable
production ML models | product features
Required skills
UVM methodology, System-level verification, Block-level verification, Verification planning, Coverage analysis, Testbench development, State machine modeling, Performance optimization, Reusability engineering, Design for testability
Preferred skills
DDR5/DDR6 architecture knowledge, Advanced verification environment optimization, Feasibility study analysis
Technologies
UVM, System-level testbenches, Block-level testbenches
Responsibilities
Define verification strategy, test plans, and coverage goals; Execute tests and monitor coverage; Collaborate with design teams to ensure requirements and testability; Drive process improvements for quality and efficiency; Report status to management.
Seniority
Senior Staff, hands-on IC
