Senior Staff DFT Engineer
Core
Define and document comprehensive DFT architecture for multi-core SoCs, lead integration of digital subsystems, perform scan insertion, and generate ATPG patterns to ensure high fault coverage for next-generation Mobile Power ICs.
Role type
Sr. Staff DFT Design Engineer (Digital/Mixed-Signal)
Builds
Next-generation Mobile Application Processor SoCs and Power Management ICs
Domain
Semiconductor / Digital IC Design / Test Engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture definition, Scan compression, Memory BIST (MBIST), Functional BIST, Logic BIST, JTAG/IEEE 1149.1/1687/1838, ATPG, DFT insertion, SoC/MCU architecture, EDA tools (Synopsys, Mentor), Test mode verification, ATE validation, Yield improvement
Preferred skills
Functional Safety, Mixed-signal design (Power, Audio, RF), Non-volatile memory (Flash, MRAM, ReRAM), Production test engineering
Technologies
Synopsys TestMAX, Mentor Tessent, IEEE 1149.1, IEEE 1687, IEEE 1838, ATPG, JTAG
Responsibilities
Define DFT architecture for multi-core SoCs, Lead integration of digital subsystems and scan insertion, Generate ATPG patterns, Validate and debug test modes/patterns in lab or on ATE, Diagnose fail devices and support PFA, Work with Product/Test/Applications Engineering for product release
Seniority
Sr. Staff, hands-on IC design & architecture leadership
