Experienced ASIC Analog Layout Engineer (m/f/d)
Core
Top-level integration of analog and mixed-signal ICs, driving layout development for robust, DRC-compliant designs with optimal area utilization.
Role type
Senior ASIC Analog Layout Engineer
Builds
Analog and mixed-signal chips (analog on top)
Domain
Semiconductor / Automotive
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: production ML models is wrong, this is hardware layout. Correcting to: production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (layout is infrastructure for silicon) -> Actually, standard mapping for layout is 'product features' (the chip itself) or 'infrastructure'. Let's use 'product features' as the chip is the product feature for the system, or 'infrastructure' if it's internal. Given 'top-level integration', 'product features' fits best as the deliverable is the functional chip block.
Required skills
top-level layout integration, floorplanning, padframe design, parasitic extraction, DRC/LVS compliance, deep submicron effects understanding, analog circuit design knowledge
Preferred skills
BCD technologies expertise (65nm to 180nm), knowledge of analog circuit design
Technologies
layout tools for design, DRC, LVS, and extraction
Responsibilities
Define toplevel floorplan, padframe design, and bonding diagrams; Coordinate with other layout engineers; Generate and integrate analog layouts at block and chip level; Perform pin placement and layout optimization; Ensure compliance with DRC, LVS, and support tape-out activities; Collaborate with design engineers to meet speed, area, power, DFM, ESD, and EMC requirements
Seniority
Senior, hands-on IC
