Experienced RTL Design Engineer (3+ Years of Experience)
Core
Design and implement PAD/PFC logic for SoC products, including pin multiplexing, boundary scan, test functions, and I/O control logic.
Role type
Senior IC RTL Design Engineer (SoC PAD/PFC)
Builds
SoC products with integrated PAD/PFC logic
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features
Required skills
Verilog, SystemVerilog, Python scripting, RTL linting, CDC analysis, synthesis, timing analysis
Preferred skills
Tcl scripting, formal verification, DFT, boundary scan, backend implementation
Technologies
PGA, SCAAPII, SpyGlass Lint, CDC, Genus, DC, PrimeTime, JG-CONN, JG-CSV, JG-FPV
Responsibilities
Design PAD/PFC logic based on specifications; Generate and validate PAD logic using in-house tools; Analyze and resolve design issues from lint, CDC, synthesis, and timing tools; Develop automation scripts for design flow; Review verification and signoff results; Collaborate with verification, DFT, STA, backend, and architecture teams.
Seniority
Mid-level, hands-on IC
