Copy of (Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried )
Core
Design, develop, and qualify semiconductor package and interconnect methods for power SiP/modules, wafer level, flip-chip, and multi-chip module applications.
Role type
Staff Package Design Engineer (Power/GaN)
Builds
Power SiP/modules, wafer level packages, flip-chip interconnects, panel level packages
Domain
Semiconductor packaging for Automotive, Industrial, Infrastructure, and IoT
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Package development, power SiP/module design, wafer level packaging, flip-chip packaging, assembly process qualification, SPC, statistical analysis, DOE execution, OSAT/CM management
Preferred skills
Wire-bonding, multi-chip module technologies, GaN packaging
Technologies
SPC software, DOE tools
Responsibilities
Benchmark and qualify materials, processes, and subcontractors; develop and run DOE to optimize processes; qualify new packages and processes; address customer complaints; ensure smooth production transition and ramp-up; participate in packaging roadmap development; establish and maintain package design rules
Seniority
Staff, hands-on IC with strategic execution
