Sr. Silicon Packaging Process Engineer, Silicon Technology (Starlink)
Core
Developing in-house integrated circuit packaging and assembly processes for Starlink satellites and consumer receivers.
Role type
Senior Silicon Packaging Process Engineer
Builds
Wafer-level and chip-level packaging systems for satellite constellations and broadband receivers
Domain
Aerospace / Semiconductor Manufacturing
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor assembly and packaging process development, equipment selection, material selection, NPI/NTI execution, cross-functional interface with IC design and thermal teams, yield and reliability optimization
Preferred skills
Advanced packaging technologies (flip-chip, BGA, fcCSP, WLCSP, fan out FO, SiP, MCM, panel level packaging, chiplet integration), OSAT experience, PCB/PCBA/SMT assembly expertise
Technologies
Wafer grinding, dicing, lithography, lamination, plating, etching, SMT, flip chip, bonding, molding, underfill, dispense, sputter, lid attach, solder ball attach
Responsibilities
Own packaging assembly processes from concept to mass production, develop new technologies and establish baselines for assembly, bring-up new product and technology introductions, select equipment and materials to meet quality and cost targets, interface with suppliers for continuous improvement, cross-functional collaboration with design and production teams
Seniority
Senior, hands-on IC