(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried )
Core
Design, develop, and qualify semiconductor packaging solutions for power SiP/modules, wafer level, flip-chip, and GaN devices, ensuring superior quality for automotive, industrial, and IoT applications.
Role type
Staff Package Design Engineer (Power/GaN)
Builds
Power SiP/modules, wafer level packages, flip-chip interconnects, panel level packages, and multi-chip modules
Domain
Semiconductor packaging (Power, GaN, Automotive, Industrial, IoT)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Package development for power SiP/modules, wafer level packaging, flip-chip packaging, assembly process qualification, SPC, statistical analysis, DOE execution, OSAT/CM management
Preferred skills
Wire-bonding, multi-chip module technologies, GaN packaging knowledge
Technologies
SPC software, DOE tools, OSAT/CM platforms
Responsibilities
Benchmark and qualify materials, processes, and subcontractors; Develop and run DOE to optimize processes and resolve issues; Qualify new packages and address customer complaints; Ensure smooth production transition and ramp-up monitoring; Participate in packaging roadmap development and maintain technical expertise on innovations; Establish and maintain package design rules
Seniority
Staff, hands-on IC with strategic oversight
